Semiconductor device manufacturing method thereof

ABSTRACT

The present invention relates to a semiconductor device including a high withstand voltage MOS transistor and a manufacturing method thereof. The semiconductor device according to the present invention includes a MOS transistor in which a second-conductivity type source region is formed on a first-conductivity type semiconductor region, an offset drain region is interconnected to a second-conductivity type drain region and has a concentration lower than an impurity concentration of a drain region, the offset drain region is composed of a portion that does not overlap a first-conductivity type semiconductor region and a portion that overlaps part of the surface of the first-conductivity type semiconductor region and a gate electrode is formed on the surface extending from a channel region between the source region and the offset drain region to part of the offset drain region through a gate insulating film. 
     Thus, there can be obtained an offset drain type MOS transistor having a stable threshold voltage Vth and a low ON-state resistance.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device including a highwithstand voltage MOS transistor and a manufacturing method thereof, andmore particularly to a semiconductor device including a high withstandvoltage MOS transistor having an offset-drain structure and amanufacturing method thereof.

BACKGROUND ART

In recent years, markets of displays are rapidly expanding as personalcomputers and home television receivers are becoming larger in size. Atpresent, in the field of displays, cathode-ray tubes are most populardisplays because they are excellent in visibility, such ashigh-definition, high-intensity, a wide angle of view and high contrast.On the other hand, as displays are becoming larger in size, such largerdisplays need larger areas and this increase of area receives aremarkable attention. Therefore, in addition to liquid-crystal displaysand projector displays, flat panel displays such as organicelectroluminescence displays that can decrease their thickness much morehave been so far expected as next-generation displays instead of thecathode-ray tubes. In accordance therewith, also in the fields ofsemiconductors, a demand for a high withstand voltage process that canform high withstand voltage driving ICs, e.g. high withstand voltagedisplay driver ICs is increasing.

A MOS transistor having a conventional structure, for example, has aso-called symmetrical arrangement in which second-conductivity typesource region and drain region are formed on a first-conductivity typesemiconductor well region serving as a back-gate region and a gateelectrode is formed on the surface of the semiconductor well regionbetween the source region and the drain region through a gate insulatingfilm, although not shown. In such MOS transistor, as the gate lengthdecreases, a resistance component in the channel region decreases sothat the MOS transistor can operate at higher speeds. In the MOStransistor having the above-mentioned structure, however, if the gatelength decreases in order to increase operation speed, then when a drainvoltage increases, a depletion layer from the drain region reaches thesource region to cause a breakdown and hence a withstand voltage cannotbe obtained.

Accordingly, as the high withstand voltage MOS transistor, there hasbeen so far developed an offset drain type lateral operation MOStransistor in which a source-drain withstand voltage can increase, i.e.a transistor called an LD (lateral diffused) MOS transistor. FIG. 8shows an example of an offset drain type high withstand voltage MOStransistor. This example is applied to an n-channel MOS transistor. Thishigh withstand voltage MOS transistor 18 has a structure in which anoffset drain region 20 formed of a lightly-doped n⁻ semiconductor regionis fabricated into a p-type semiconductor well region 6 that serves as aback-gate electrode. Specifically, after an n-type epitaxial layer 5 hadbeen epitaxially deposited on a first-conductivity type, e.g. p-typesilicon semiconductor substrate 2 through a second-conductivity typen-type buried layer 4, an element separation region e.g. element formingregion separated by a field insulating layer 3 formed by selectiveoxidation (so-called LOCOS) is formed. A p-type semiconductor wellregion 6 is formed within this element forming region to oppose thesurface such that it may contact with the n-type buried layer 4. An n⁻semiconductor region having an impurity concentration lower than that ofa drain region 8D, e.g. so-called off-set drain region 20 is formedwithin this p-type semiconductor well region 6. Then, a heavily-doped n⁺source region 8S is formed within the p-type semiconductor well region 6and a heavily-doped n⁺ drain region 8D is formed distant from the gatewithin the offset drain region 20. A gate electrode 10 is formed on thesurface of a channel region 8C formed of the p-type semiconductor wellregion 6 between the source region 8S and the offset drain region 20through an insulating gate film 9. A source electrode 11S and a drainelectrode 11D are interconnected to the source electrode 8S and thedrain electrode 8D, respectively. Reference numeral 12 denotes aninsulating film made of a suitable material such as SiO₂. The highwithstand voltage MOS transistor is constructed in this manner. In theoffset drain type high withstand voltage MOS transistor 18, an electricfield can be relaxed and a withstand voltage can be increased byexpanding a depletion layer generated by applying a drain voltage to theside of the offset drain region 20 formed of the lightly-doped n⁻semiconductor region. In the high withstand voltage MOS transistor 18shown in FIG. 8, another process for forming the offset drain region 20should be added.

On the other hand, there has been proposed an offset drain type highwithstand voltage MOS transistor having a structure that can bemanufactured with the existing processes without addition of processeswhen the offset drain type high withstand voltage MOS transistor isapplied to a CMOS transistor. FIG. 7A shows a fundamental structure ofan offset drain type high withstand voltage MOS transistor that can bemanufactured with the existing processes of the CMOS transistor.

This high withstand voltage MOS transistor 1 is formed within an elementseparation region, e.g. an element forming region separated by a fieldinsulating layer 3 formed by selective oxidation (so-called LOCOS) afteran n-type epitaxial layer 5 had been epitaxially deposited on afirst-conductivity type, e.g. p-type silicon semiconductor substrate 2through a second-conductivity type, e.g. n-type buried layer 4.Specifically, a p-type semiconductor well region 6 serving as aback-gate region and an n⁻ semiconductor region having a concentrationlower than an impurity concentration of the drain region, i.e. so-calledoffset drain region 7 are formed within this element forming region tooppose the surface such that they may contact with the n-type buriedlayer 4. A p-type element forming layer beneath the field insulatinglayer 3, i.e. so-called channel stopper layer 19 is formed with the sameprocess at the same time the p-type well region 6 is formed. Aheavily-doped n⁺ source region 8S is formed within the p-typesemiconductor well region 6 and a heavily-doped n⁺ drain region 8D isformed distant from the gate within the n⁻ semiconductor region 7 thatis the offset drain region. Then, a gate electrode 10 is formed on asurface extending from a channel 8 c formed of the P-type semiconductorwell region to a part of the n⁻ semiconductor region 7 that is theoffset drain region. A source electrode 11S and a drain electrode 11Dare respectively interconnected to the source region 8S and the drainregion 8D. Reference numeral 12 denotes an insulating film made of asuitable material such as SiO₂. The high withstand voltage MOStransistor 1 is constructed in this manner.

In this high withstand voltage MOS transistor 1, similarly as describedabove, when a reverse bias is applied between the source electrode 11Sand the drain electrode 11D, the depletion layer expands from a pnjunction between the p-type semiconductor well region 6 and the offsetdrain region (also referred to as a “drift region”) formed of the n⁻semiconductor region to the n⁻ semiconductor region 7. The electricfield is relaxed by using the expansion of the depletion layer towardthe n semiconductor region 7, whereby the withstand voltage of the MOStransistor can be maintained.

When the above-mentioned high withstand voltage MOS transistor 1 isapplied to the CMOS transistor, the above-described offset drain region7 comprising one second-conductivity type channel MOS transistor isformed at the same time a semiconductor well region serving as aback-gate region in the other first-conductivity type channel MOStransistor formed in other region, not shown, is formed. Specifically,when the high withstand voltage MOS transistor 1 is formed as onen-channel MOS transistor comprising the CMOS transistor, the offsetdrain region 7 formed of the lightly-doped n⁻ semiconductor regioninterconnected to the n⁺ drain region 8D is formed at the same time inthe process in which the n-type semiconductor well region serving as theback-gate of the other p-channel MOS transistor comprising the CMOStransistor is formed. Consequently, it is possible to manufacture theCMOS transistor including the offset drain type high withstand voltageMOS transistor with the number of the existing processes.

In the above-mentioned high withstand voltage MOS transistor 1, sinceone process serves both as the process for forming the elementseparation layer (p-type channel stopper layer) 19 and the process forforming the p-type semiconductor well region 6, after the n-typeepitaxial layer 5 had been epitaxially deposited and the fieldinsulating layer 3 had been formed as shown in FIG. 7B, the elementseparation layer 19 and the p-type semiconductor well region 6 areformed at the same time. Specifically, after the field insulating layer3 had been formed, a photoresist mask 14 having an opening 14 a across apart of the field insulating layer 3 and an opening 14 b located on thefield insulating layer 3 is formed by patterning a positive typephotoresist film, for example, and the p-type semiconductor well region6 and the element separation layer (p-type channel stopper layer) 19 areformed by implanting ions of p-type impurities, e.g. ions of boron 15through this photoresist mask 14. Having considered the case in whichthe element separation layer 19 is formed, ion implantation conditionsare designed in such a manner that the impurity concentration may reacha peak 15 on the surface (accordingly, the depth position) of the n-typeepitaxial layer 5 beneath the field insulating layer 3. In the positivetype photoresist mask 14, the end portions of the opening portions 14 a,14 b are formed like tapered end portions as illustrated in order toprevent interference of light required when the photoresist film isexposed thereto.

In the above-mentioned high withstand voltage MOS transistor 1, thefield insulating layer 3 has a film thickness of approximately 800 nm,for example, and energy for implanting ions is approximately 360 keV.The film thickness of the photoresist mask 14 should increase as energyfor implanting ions increases as described above, and the photoresistmask needs a film thickness of about 2.4 μm. One process can serve bothas one process and the other process by optimizing the processconditions as described above.

However, there arises a serious problem that the threshold voltage Vthbecomes larger than a designed value and is fluctuated as energy forimplanting ions increases. Specifically, when energy for implanting ionsis large as shown in FIG. 7B, the impurity ions 16 are caused to gothrough the photoresist mask 14 at the opening end portions (tapered endportions) of the photoresist mask 14 in the element forming region sideso that the impurity concentration peak 15 moves near the surface of then-type epitaxial layer 5 along the angle of the tapered opening endportion of the photoresist mask 14, thereby resulting in a heavily-dopedimpurity region 17 (see FIG. 7A) that exerts a serious influence uponthe threshold voltage Vth.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductordevice including a high withstand voltage MOS transistor in which aheavily-doped impurity region can be prevented from being formed at oneportion of a channel region and in which a high withstand voltage, astable threshold voltage Vth and a low ON-state resistance can be madecompatible and a manufacturing method thereof.

A semiconductor device according to the present invention includes a MOStransistor in which a second-conductivity type source region is formedat a first-conductivity type semiconductor region and electricallyinterconnected to a second-conductivity type drain region, an offsetdrain region having an impurity concentration lower than that of thedrain region is formed, the offset drain region comprises a portion thatdoes not overlap the first-conductivity type semiconductor region and aportion that overlaps part of the surface of the first-conductivity typesemiconductor region and a gate electrode is formed on the surfaceextending from a channel region between the source region and the offsetdrain region to part of the offset drain region through a gateinsulating film.

The offset drain region is formed at its portion that overlaps part ofthe surface of the first-conductivity type semiconductor region by aregion in which a first-conductivity type impurity introduced region iscanceled out by a second-conductivity type impurity. Therefore, theportion in which the offset drain region does not overlap thefirst-conductivity type semiconductor region and the portion in whichthe offset drain region overlaps part of the surface of thefirst-conductivity type semiconductor region can be both formed in alightly-doped second-conductivity type region.

Further, the portion in which the offset drain region does not overlapthe first-conductivity type semiconductor region is formed of asecond-conductivity type region and the portion in which the offsetdrain region overlaps part of the surface of a first-conductivity typesemiconductor region is formed of a first-conductivity type regionhaving an impurity concentration lower than that of thefirst-conductivity type semiconductor region.

The whole area of the channel region between the source region and theoffset drain region, i.e. the channel region on the surface of thefirst-conductivity type semiconductor region is formed in a uniformconcentration.

The above-described MOS transistor includes a first-conductivity typeelement separation layer (so-called channel stopper layer) that isformed beneath a separation region for separating the MOS transistor atthe same time the first-conductivity type semiconductor region isformed. In this case, the separation region can be formed of a fieldinsulating layer by selective oxidation and the first-conductivity typesemiconductor region and the first-conductivity type element separationlayer can be formed by implanting ions such that the semiconductorsurface beneath the field insulating layer reaches an impurityconcentration peak.

When the semiconductor device according to the present invention isapplied to a semiconductor device including a CMOS transistor, theoffset drain type MOS transistor having the above-described arrangementis formed as one second-conductivity type channel MOS transistorcomprising a CMOS transistor, a first-conductivity type semiconductorregion of the second-conductivity type channel MOS transistor is formedas a back-gate region and the offset drain region is formed at the sametime the back-gate region of the other first-conductivity type channelMOS transistor comprising the CMOS transistor is formed.

A semiconductor device manufacturing method according to the presentinvention is comprised of the steps of a process for forming aseparation region for separating an element forming region on asemiconductor base, a process for forming a first-conductivity typesemiconductor region on the element forming region, a process forforming an offset drain region comprising a portion that does notoverlap the first-conductivity type semiconductor region and a portionthat overlaps part of the surface of the first-conductivity typesemiconductor region and which has an impurity concentration lower thanthat of a drain region, a process for forming second-conductivity typesource region and drain region on the first-conductivity typesemiconductor region and the offset drain region, respectively, and aprocess for forming a gate electrode on a surface extending from achannel region comprised of the first-conductivity type semiconductorregion between the source region and the offset drain region to theoffset drain region through a gate insulating film.

A semiconductor device manufacturing method according to the presentinvention is comprised of the steps of a process for forming a fieldinsulating layer formed by selective oxidation for separating an elementforming region after a second-conductivity type buried region had beenformed on a first-conductivity type semiconductor substrate and asecond-conductivity type epitaxial layer had been formed, a process forforming a first-conductivity type semiconductor region on the elementforming region, a process for forming an offset drain region having animpurity concentration lower than that of a drain region by introducingsecond-conductivity impurities over a portion that does not overlap thefirst-conductivity type semiconductor region and a portion that overlapspart of the surface of the first-conductivity type semiconductor region,a process for forming second-conductivity type source region and drainregion on the first-conductivity type semiconductor region and theoffset drain region, respectively, and a process for forming a gateelectrode on a surface extending from a channel region composed of thefirst-conductivity type semiconductor region between the source regionand the offset drain region to the offset drain region through a gateinsulating film.

The portion in which the offset drain region does not overlap thefirst-conductivity type semiconductor region and the portion in whichthe offset drain region overlaps part of the surface of thefirst-conductivity type semiconductor region are both formed so as toserve as lightly-doped second-conductivity type regions. Further, theportion in which the offset drain region does not overlap thefirst-conductivity type semiconductor region may be formed so as toserve as a second-conductivity type region and the portion in which theoffset drain region overlaps part of the surface of thefirst-conductivity type semiconductor region is formed so as to serve asa first-conductivity type region having an impurity concentration lowerthan that of the first-conductivity type semiconductor region.

According to the present invention, the first-conductivity typesemiconductor region and the offset drain region can be formed by ionsof second-conductivity type impurities and by heat treatment foractivation after ions of first-conductivity type impurities had beenimplanted. At that time, the ions of the second-conductivity typeimpurities are implanted with a dose large enough to cancel an impurityconcentration peak portion on the surface side after the ions of thefirst-conductivity type impurities had been implanted.

When the first-conductivity type semiconductor region, the offset drainregion, the source region and the drain region are formed, thefirst-conductivity type semiconductor region and the offset drain regioncan be formed by implanting ions of first-conductivity type impuritieswith a dose of 1×10¹³ to 1×10¹⁴ cm⁻² and by implanting ions ofsecond-conductivity type impurities with a dose of 5×10¹² to 1×10¹⁴ cm⁻²and the second-conductivity type source region and drain region can beformed by implanting ions of second-conductivity type impurities with adose of 1×10¹⁵ to 1×10¹⁶ cm⁻².

The first-conductivity type semiconductor region and afirst-conductivity type element separation layer beneath the separationregion are formed at the same time. At that time, the first-conductivitytype semiconductor region and a first-conductivity type elementseparation layer beneath the separation region are formed at the sametime by introducing first-conductivity type impurities such that thesemiconductor surface beneath the separation region reaches an impurityconcentration peak obtained when ions are implanted. When ions areimplanted, the first-conductivity type semiconductor region, afirst-conductivity type element separation layer beneath the separationregion and the offset drain region are formed at the same time byimplanting ions of first-conductivity type impurities through a positivetype photoresist mask whose opening end portion is tapered and byimplanting ions of second-conductivity type impurities through apositive type photoresist mask whose opening end portion is tapered.

The whole area of the channel region between the source region and theoffset drain region, i.e. the channel region on the surface of thefirst-conductivity type semiconductor region is formed with a uniformconcentration.

When the semiconductor device manufacturing method according to thepresent invention is applied to a manufacturing process of asemiconductor device including a CMOS transistor, the first-conductivitytype semiconductor region is formed as a back-gate region of onesecond-conductivity type channel MOS transistor comprising the CMOStransistor and the offset drain region is formed at the same time aback-gate region of the other first-conductivity type channel MOStransistor comprising the CMOS transistor is formed.

According to the semiconductor device of the present invention, sincethe lightly-doped offset drain region comprising the portion that doesnot overlap the first-conductivity type semiconductor region and theportion that overlaps part of the surface of the first-conductivity typesemiconductor region is formed in the MOS transistor having the offsetdrain structure, the heavily-doped impurity region formed at the aboveone portion on the surface of the first-conductivity type semiconductorregion is canceled out and removed by the offset drain region. As aresult, the whole area of substantially the channel region formed by thefirst conductivity-type semiconductor region between the source regionand the offset drain region is formed with a uniform low concentration.Thus, the threshold voltage Vth can be prevented from becoming largerthan a design value and can also be prevented from being fluctuated sothat the stable threshold voltage Vth and the stable low ON-stateresistance can be obtained. Therefore, it becomes possible to realizethe MOS transistor having the offset drain structure in which the highwithstand voltage, the stable threshold voltage Vth and the stable lowON-state resistance can be made compatible.

The portion that overlaps part of the surface of the first-conductivitytype semiconductor region of the offset drain region is formed of theregion in which the first-conductivity type impurity introduced regionis canceled by the second-conductivity type impurities. Thus, when theoffset drain region is formed such that the portion that overlaps partof the surface of the first-conductivity type semiconductor region andthe portion that does not overlap he first-conductivity typesemiconductor region are formed as the lightly-doped second-conductivitytype semiconductor regions, the whole area of the channel region isdoped uniformly so that the stable threshold voltage Vth can be obtainedas it is designed. Moreover, even when the portion in which the offsetdrain region overlaps the first-conductivity type semiconductor regionis formed as the first-conductivity type region, since it is formed bythe region having the concentration lower than the impurityconcentration of the first-conductivity type semiconductor region, thesubstantially threshold voltage Vth is determined by the heavily-dopedfirst conductivity-type semiconductor region between the source regionand the offset drain region, i.e. the channel region and hence thestable threshold voltage Vth can be obtained as it is designed.

Since the first-conductivity type semiconductor region and thefirst-conductivity type element separating layer (so-called channelstopper layer) beneath the separation region are formed at the sametime, the manufacturing process can be simplified. Then, when theseparation region is formed of the field insulating layer by selectiveoxidation and the first-conductivity type semiconductor region and thefirst-conductivity type element separation layer are formed at the sametime by ion implantations such that the semiconductor surface beneaththe field insulating layer may reach the peak of the impurityconcentration, since this transistor includes the above-described offsetdrain region, unnecessary heavily-dope region is not formed on thesurface side and hence the stable threshold voltage Vth can be obtained.

When the MOS transistor of the present invention is applied to the CMOStransistor, the MOS transistor with the offset drain structure havingthe above-described arrangement is formed as one second-conductivitytype channel MOS transistor comprising the CMOS transistor, thefirst-conductivity type semiconductor region of this second-conductivitytype channel MOS transistor is formed as the back-gate region and theoffset drain region is formed at the same time the back-gate region ofthe other first-conductivity type channel MOS transistor comprising theCMOS transistor is formed, whereby the high withstand voltage CMOStransistor can be obtained through the existing number of processeswithout addition of processes.

According to the semiconductor device manufacturing method of thepresent invention, since the manufacturing process of the MOS transistorhaving the offset drain structure includes a series of theabove-mentioned processes, in particular, the process for forming theoffset drain region comprising the portion that does not overlap thefirst-conductivity type semiconductor region and the portion thatoverlaps part of the surface of the first-conductivity typesemiconductor region and which has the impurity concentration lower thanthat of the drain region, the heavily-doped region formed on the aboveone portion of the surface of the channel region side of thefirst-conductivity type semiconductor region is canceled out and removedby the offset drain region, and hence the concentration of substantiallythe channel region formed by the first-conductivity type semiconductorregion between the source region and the offset drain region can be madeuniform on the whole area. Accordingly, the threshold voltage Vth can beprevented from becoming larger than the design value or can be preventedfrom being fluctuated. Also, the highly-efficient and high withstandvoltage MOS transistor having the offset drain structure in which thestable threshold voltage Vth and the low ON-state resistance are madecompatible can be easily manufactured with high reliability.

Since the offset drain region is formed such that the portion that doesnot overlap the first-conductivity type semiconductor region and theportion that overlaps part of the surface of the first-conductivity typesemiconductor region are both formed as the lightly-dopedsecond-conductivity type semiconductor regions, the MOS transistor withthe offset drain structure having the above-described stable thresholdvoltage Vth and low ON-state resistance can be manufactured. Further,when the offset drain region is formed such that the portion that doesnot overlap the first-conductivity type semiconductor region is formedas the second-conductivity type semiconductor region and the portionthat overlaps part of the surface of the first-conductivity typesemiconductor region is formed as the first-conductivity typesemiconductor region having the concentration lower than the impurityconcentration of the first-conductivity type semiconductor region, theportion that overlaps the first-conductivity type semiconductor regionacts as the offset drain region, and hence the MOS transistor with theoffset drain structure having the above-described threshold voltage Vthand low ON-state resistance can be manufactured.

When the first-conductivity type semiconductor region and the offsetdrain region are formed simultaneously by implanting ions ofsecond-conductivity type impurities and by heat treatment for activationafter ions of first-conductivity type impurities had been implanted, themanufacturing process can be simplified. At that time, when ions ofsecond-conductivity type impurities are implanted with a dose largeenough to cancel the impurity concentration peak generated at portion onthe surface side out after ions of first-conductivity type impuritieshad been implanted, the first-conductivity type heavily-doped region isnot formed at the portion corresponding to the first-conductivity typeimpurity concentration peak generated at portion on the above-describedsurface side and substantially the channel region in which theconcentration can be made uniform in the whole area can be formed.

When the first-conductivity type semiconductor region and the offsetdrain region are formed, the above-mentioned offset drain region and thefirst-conductivity type semiconductor region including the channelregion in which the concentration is made uniform in the whole area canbe formed by implanting ions of first-conductivity type impurities of adose of 1×10¹³ to 1×10¹⁴ cm⁻² and by implanting ions ofsecond-conductivity type impurities of a dose of 5×10¹² to 1×10¹⁴ cm⁻².Further, since the second-conductivity type source region and drainregion are formed by implanting ions of second-conductivity typeimpurities of a dose of 1×10¹⁵ to 1×10¹⁶ cm⁻², not only theabove-described first-conductivity type semiconductor region and theoffset drain region can be formed but also the MOS transistor with theabove-mentioned offset drain structure can be manufactured.

Since the first-conductivity type semiconductor region and thefirst-conductivity type element separation layer beneath the separationlayer are formed at the same time, the number of manufacturing processescan decrease and the manufacturing process can be simplified. When thefirst-conductivity type semiconductor region and the first-conductivitytype element separation layer are simultaneously formed by introducingfirst-conductivity type impurities such that the semiconductor surfacebeneath the separation region may reach the impurity concentration peakobtained when ions are implanted, since the offset drain region isformed as described above, unnecessary heavily-doped region can beprevented from being formed on the surface of the channel region side.When the positive type photoresist mask is used as the mask forimplanting ions, although the opening portion end is tapered and theconcentration peak of the first-conductivity type impurity reaches thesurface side at this tapered portion, since the offset drain region isformed as described above, unnecessary heavily-doped impurity region canbe prevented from being formed on the surface of the channel regionside.

When the MOS transistor manufacturing method according to the presentinvention is applied to the manufacturing process of the CMOStransistor, since the first-conductivity type semiconductor region isformed as the back-gate region of one second-conductivity type channelMOS transistor comprising the CMOS transistor and the above-describedoffset drain region is formed at the same time the back-gate region ofthe other first-conductivity type channel MOS transistor comprising theCMOS transistor is formed, it becomes possible to manufacture thesemiconductor device having the CMOS transistor in which at least oneMOS transistor has the offset drain structure in which this transistoris the high withstand voltage transistor and which has the stablethreshold voltage Vth and the low ON-state resistance.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram showing an arrangement of a semiconductor device,particularly, its high withstand voltage MOS transistor according to anembodiment of the present invention.

FIGS. 2A to 2C are manufacturing process diagrams (No. 1) showing amanufacturing method of a semiconductor device, particularly, its highwithstand voltage MOS transistor according to an embodiment of thepresent invention.

FIGS. 3A to 3C are manufacturing process diagrams (No. 2) showing amanufacturing method of a semiconductor device, particularly, its highwithstand voltage MOS transistor according to an embodiment of thepresent invention.

FIGS. 4A and 4B are manufacturing process diagrams (No. 3) showing amanufacturing method of a semiconductor device, particularly, its highwithstand voltage MOS transistor according to an embodiment of thepresent invention.

FIGS. 5A to 5C are manufacturing process diagrams (No. 4) showing amanufacturing method of a semiconductor device, particularly, its highwithstand voltage MOS transistor according to an embodiment of thepresent invention.

FIGS. 6A and 6B are manufacturing process diagrams (No. 5) showing amanufacturing method of a semiconductor device, particularly, its highwithstand voltage MOS transistor according to an embodiment of thepresent invention.

FIG. 7A is a diagram showing an arrangement of an example of asemiconductor device, in particular, its high withstand voltage MOStransistor according to the prior art.

FIG. 7B is a process diagram showing a process somewhere in themanufacturing process of FIG. 7A.

FIG. 8 is a diagram showing an arrangement of another example of asemiconductor device, in particular, its high withstand voltage MOStransistor according to the prior art.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

Embodiments according to the present invention will be described belowwith reference to the drawings.

FIG. 1 shows a semiconductor device, in particular, a highly-efficientand high withstand voltage MOS transistor according to an embodiment ofthe present invention.

A high withstand voltage MOS transistor 21 according to this embodimentis a MOS transistor having an offset drain structure. This highwithstand voltage MOS transistor 21 is formed on an element separationregion, in this embodiment, an element forming region separated by afield insulating layer 25 formed by selective oxidation (LOCOS) after ann-type epitaxial layer 24 had been deposited on a first-conductivitytype, e.g. p-type silicon semiconductor substrate 22 through an n-typeburied layer 23. Specifically, a p-type semiconductor well region 26 isformed to oppose the n-type buried layer 23 and an offset drain region27 having an impurity concentration lower than that of a drain region isformed. This offset drain region 27 comprises a portion that doe notoverlap the p-type semiconductor well region 26 and a portion thatoverlaps part of the surface of the p-type semiconductor well region 26.The offset drain region 27 is formed by introducing n-type impuritiesand the portion that overlaps part of the surface of the p-typesemiconductor well region is formed by a region in which the p-typeimpurity introduced region is canceled by n-type impurities.Accordingly, in the offset drain region 27, both of the portion thatdoes not overlap the p-type semiconductor well region 26 and the portionthat overlaps part of the surface of the p-type semiconductor wellregion 26 can be formed by semiconductor regions of low concentration,i.e. so-called n⁻ semiconductor regions. Moreover, the offset drainregion 27 can be formed in such a manner that the portion that does notoverlap the p-type semiconductor well region 23 becomes a n⁻semiconductor region and that the portion that overlaps part of thesurface of the p-type semiconductor well region 23 becomes a p-typesemiconductor region (e.g. p⁻⁻ region) having an impurity concentrationlower than that of the p-type semiconductor well region 26. This offsetdrain region 27 is also called a drift region. A p-type elementseparation layer (so-called p-type channel stopper layer) 33 is formedbeneath the field insulating layer 25. This p-type element separationlayer 33 is formed at the same time the p-type semiconductor well region26 is formed.

A heavily-doped n⁺ source region 22S is formed on the surface of thep-type semiconductor well region 26. A heavily-doped n⁺ drain region 28Dis formed on the surface of the offset drain region 27 formed of an n⁻semiconductor region. Then, a gate electrode 30 is formed on the surfaceextending from a channel region 28C on the surface of the p-typesemiconductor well region 26 to part of the offset drain region 27through a gate insulating film 29 so as to adjoin the end of the n⁺source region 28S. The n⁺ drain region 28D is formed at the positiondistant from the gate insulating film 29 and the other end of the gateelectrode 30. An insulating film 32 formed of an SiO₂ film, for example,is formed on the whole surface including the gate electrode 30, and asource electrode 32S and a drain electrode 32D are interconnected to then⁺ source region 28S and the n⁺ drain region 28D through contact holesformed on the insulating film 31, respectively. The field insulatinglayer 25 and the p-type channel stopper layer 33 formed beneath thefield insulating layer constitute a substantially element separationregion. In this manner, there is fabricated the high withstand voltageMOS transistor 21 according to this embodiment.

When this high withstand voltage MOS transistor 21 is applied to a CMOStransistor, the offset drain region 27 comprising onesecond-conductivity type channel MOS transistor is formed at the sametime a second-conductivity type semiconductor well region that serves asa back-gate region in a first-conductivity type channel MOS transistorformed on other region, though not shown, is formed. Specifically, whenthe high withstand voltage MOS transistor 21 is one n-channel MOStransistor comprising the CMOS transistor, the offset drain region 27formed of a lightly-doped n⁻ semiconductor region electricallyinterconnected to the n⁺ drain region 28D is formed at the same time ann-type semiconductor well region serving as a back-gate region of otherp-channel MOS transistor comprising the CMOS transistor is formed.

FIGS. 2 to 6 show a manufacturing method of the above-mentioned highwithstand voltage MOS transistor 21 according to the embodiment.

First, as shown in FIG. 2A, a first-conductivity type, e.g. p-typesilicon semiconductor substrate 22 is prepared, and an insulating film41 having a predetermined thickness is formed on one major surface ofthis semiconductor substrate 22 by thermal oxidation. In thisembodiment, the SiO₂ film 41 having a thickness ranging fromapproximately 30 nm to 50 nm is formed by steam oxidation at atemperature ranging from approximately 900° C. to 1000° C. Next, aphotoresist mask 42 having an opening 42 a formed at its portioncorresponding to the element forming region is formed by usingphotolithography technique and ion-implantation technique. An n-type ionimplanted region 23A is formed on the p-type semiconductor substrate 22by implanting ions of second-conductivity type impurities, i.e. n-typeimpurities 40 through this photoresist mask 42.

In this embodiment, ions of phosphorous (P) 40 having a dose rangingapproximately 1×10¹³ to 5×10¹³ cm² are implanted. Then, as shown in FIG.2B, after the photoresist mask 42 had been removed, the n-type buriedlayer 23 is formed by heat treatment at a temperature ranging fromapproximately 950° C. to 1000° C.

Next, as shown in FIG. 2C, the insulating film 41 formed by thermaloxidation is removed and an n-type epitaxial layer 24 having apredetermined resistivity, in this embodiment, 5 to 10 Ωcm isepitaxially deposited on the semiconductor substrate. The semiconductorsubstrate 22, the n-type buried layer 23 and the n-type epitaxial layer24 constitute the semiconductor base.

Next, as shown in FIG. 3A, a silicon oxide film 43 is formed on thesurface of the n-type epitaxial layer 24 by thermal oxidation. In thisembodiment, the SiO₂ film 43 having a film thickness ranging from 60 nmto 100 nm is formed by steam oxidation at a temperature ranging fromapproximately 900° C. to 950° C.

Subsequently, a silicon nitride film 44 is formed on the SiO₂ film 43 byreduced CVD (chemical vapor growth). In this embodiment, there is formedthe Si₃N₄ film 44 having a film thickness ranging from approximately 80nm to 100 nm.

Next, as shown in FIG. 3B, a photoresist mask 45 is formed on the regioncorresponding to an element forming region (so-called active region) inwhich the target high withstand voltage MOS transistor should be formedby photolithography technique. Then, part of the surfaces of the Si₃N₄film 44, the SiO₂ film 43 and the n-type epitaxial layer 24 isselectively etched away by anisotropy etching technique such as RIE(reactive ion etching).

Next, after the photoresist mask 45 had been removed, as shown in FIG.3C, the field insulating layer 25 is formed by selective oxidation(LOCOS) treatment. In this embodiment, there is formed the silicon oxidelayer 25 having an oxidation film thickness ranging from approximately600 nm to 900 nm by steam oxidation at a temperature ranging fromapproximately 950° C. to 1000° C. At that time, since the surface of theepitaxial layer 24 in the region that is selectively oxidized in advanceis selectively removed, the field insulating layer 25 becomes flush withthe epitaxial layer 24. A region encircled by the field insulating layer25 serves as the element forming region 46. Subsequently, the Si₃N₄ film44 is removed by hot phosphoric acid. Further, after the SiO₂ film hadbeen removed from the surface of the n-type epitaxial layer 24 bychemicals dissolved water containing hydrogen fluoride (HF), a heatoxide film, in this embodiment, an SiO₂ film 47 having a film thicknessranging from approximately 20 nm to 50 nm is formed again by steamoxidation at a temperature ranging from 950° C. to 1000° C.

Next, as shown in FIG. 4A, ions of p-type impurities 49 are implanted tothe semiconductor region beneath part of the field insulating layer 25that will be formed later on and a region corresponding to the p-typesemiconductor well region that serves as an active region byphotolithography technique and ion implantation technique.

Specifically, after the field insulating layer 25 had been formed, aphotoresist mask 48 having an opening 48 a extending from a half of theelement forming region 46 to part of the field insulating layer 25 ofone side and an opening 48 b located on the field insulating layer 25 isformed by patterning a positive type photoresist film, for example.Since the photoresist mask 48 is the positive type photoresist mask, theopening end portions of the openings 48 a, 48 b are tapered asillustrated.

Subsequently, ions of p-type impurities are implanted through thisphotoresist mask 48. In this embodiment, ions of boron (B) 49 having adose ranging from approximately 1×10¹³ to 1×10¹⁴ cm⁻² are implanted.Ions of boron 49 are implanted such that the boron concentration reachesa peak 50 on the surface of the n-type epitaxial layer beneath the fieldinsulating layer 25, in the active region, the surface of the n⁺ buriedlayer 23 (accordingly, its depth position). Accordingly, in the activeregion beneath the opening end portion (tapered end portion) of thephotoresist mask 48, ions of boron are caused to go through thephotoresist mask 48 so that the boron concentration peak 50 is movednear the surface of the n-type epitaxial layer 24 along the taperedangle of the photoresist mask 48.

Next, the photoresist mask 48 is removed, and as shown in FIG. 4B, ionsof n-type impurities 56 are implanted on the region corresponding to thelightly-doped offset drain region that will be formed later on by usingphotolithography technique and ion implantation technique one more time.

Specifically, a positive type photoresist mask 51, for example, isformed and ions of n-type impurities are implanted through thisphotoresist mask 51. Ions of n-type impurities are implanted up to thep-type impurity ion implanted region so as to cancel the concentrationpeak 50 portion from the surface side of the n-type impurity ionimplantation region in which ions had been implanted previously. In thisembodiment, ions of phosphoric (P) having a dose ranging fromapproximately 5×10¹² to 1×10¹⁴ cm⁻² are implanted. Reference numeral 57denotes a phosphoric concentration peak portion.

Next, as shown in FIG. 5A, after the photoresist mask 51 had beenremoved, by heat treatment, in this embodiment, heat treatment at atemperature ranging from approximately 1100° C. to 1200° C., the p-typechannel stopper region 33 serving as the element separation layer isformed beneath portion of the field insulating layer 25 and the p-typesemiconductor well region 26 and an n⁻ semiconductor region 27 thatserves as the offset drain region are formed on the active region at thesame time. The n⁻ semiconductor region 27 is formed such that it reachesthe n-type buried layer 23 and that part thereof overlaps part of thesurface of the p-type semiconductor well region 26 from the activeregion that does not overlap the p-type semiconductor well region 26.Although the portion in which the n⁻ semiconductor region 27 overlappart of the surface of the p-type semiconductor well region 27inherently exists on the channel region 28C on the surface of the p-typesemiconductor well region 26 and has a high concentration of p-typeimpurities, this heavily-doped portion is canceled by the n⁻semiconductor region 27. Specifically, the portion in which the n⁻semiconductor region 27 overlaps the p-type semiconductor well region 26serves as either an n⁻ region or a p⁻⁻ region depending upon a dose ofn-type impurities. Since even the p⁻⁻ region has a concentration lowerthan the impurity concentration of the p-type semiconductor well region26, the n⁻ region and the p-region substantially serve as the offsetdrain region.

The p-type semiconductor well region 26 is formed such that it may reachthe n-type buried layer 23 and that the whole area of the channel region28C on the surface may have a uniform low concentration. A SiO₂ film 52is formed on the surface of this semiconductor well region by thermaloxidation.

Next, the SiO₂ film 52 is removed from the surface by chemicalsdissolved water containing hydrogen fluoride (HF), and as shown in FIG.5B, the gate insulating film 29 and a gate electrode material film 301are sequentially formed on the whole surface including the p-typesemiconductor well region 26 and the offset drain region 27 formed ofthe n⁻ semiconductor region.

In this embodiment, the gate insulating film (SiO₂ film) 29 having afilm thickness ranging from approximately 20 nm to 50 nm is formed bysteam oxidation at a temperature ranging from approximately 950° C. to1000° C. Subsequently, there is formed the gate electrode material film301 made of an n-type impurity-doped n⁺ polycrystalline silicon filmhaving a film thickness of approximately 400 nm by CVD.

Next, as shown in FIG. 5C, the gate insulating film 29 and the gateelectrode material film 301 are selectively removed by usingphotolithography technique and anisotropy etching technique such as RIE,whereby the gate insulating film 20 and the gate electrode 30 are formedon only the gate forming region. The gate insulating film 29 and thegate electrode 30 are formed in a range extending from the channelregion 28C formed of the surface of the p-type semiconductor well region26 to part of the n⁻ semiconductor region 27.

Subsequently, after a photoresist mask (not shown) had been removed, aheat oxidation film 54 is formed on the whole surface. In thisembodiment, a silicon oxide film (SiO₂) film 54 having a film thicknessranging from approximately 10 nm to 20 nm is formed on the whole surfaceby steam oxidation at a temperature ranging from approximately 800° C.to 900° C.

Next, by using photolithography technique and ion implantationtechnique, ions of p-type impurities are implanted on a potentiallead-out region (so-called back-gate lead-out region) of the p-typesemiconductor well region 26 that serves as the back-gate region (notshown). In this embodiment, ions of boron (B) having a dose ofapproximately from 1×10¹⁵ cm⁻² are implanted.

Further, after the above-described photoresist mask had been removed,similarly by using photolithography technique and ion-implantationtechnique, ions of n-type impurities are implanted on the source formingregion of the p-type semiconductor well region 26 and the drain formingregion of the n semiconductor region 27 (not shown). In this embodiment,ions of arsenic (As) having a dose of approximately from 1×10¹⁵ to1×10¹⁶ cm⁻² are implanted.

Next, after the above-described photoresist mask (not shown) had beenremoved, as shown in FIG. 6A, an insulating film, in this embodiment, anSiO₂ film having a film thickness of approximately 600 nm was formed byCVD. Further, an n⁺ source region 28S is formed within the p-typesemiconductor well region 26 a and an n⁺ drain region 28D is formedwithin the n⁻ semiconductor region 27 by heat treatment at a temperatureranging from approximately 850° C. to 950° C. At the same time, a p⁺well region lead-out region (not shown) is formed within the p-typesemiconductor well region 26. The SiO₂ film 54 and the SiO₂ film 55constitute the insulating film 31.

Next, as shown in FIG. 6B, by using photolithography technique andanisotropy etching technique such as RIE, contact holes are formed onthe insulating film 31 at its portions corresponding to source, drainand gate lead-out regions, and the drain electrode 32D interconnected tothe drain region 28D, a p⁺ well lead-out electrode (not shown)interconnected to the p-type semiconductor well region 26 and a gatelead-out electrode (not shown) interconnected to the gate electrode 30are formed through these contact holes. The source electrode 32S, thedrain electrode 32D, the well lead-out electrode and the gate lead-outelectrode can be formed by vapor-depositing a metal film containing abarrier metal such as an Al film or a Ti/TiON/Ti/Al—Si lamination layerfilm in which Ti, TiON, Ti, Al—Si are laminated, in that order, frombelow and by patterning using photolithography technique and RIEtechnique.

In this manner, there can be obtained the target highly-efficient andhigh withstand voltage MOS transistor 21.

When the manufacturing method of the semiconductor device including theabove-mentioned high withstand voltage MOS transistor is applied to themanufacturing process of a semiconductor device including a CMOStransistor, the above-described first-conductivity type semiconductorregion 26 serves as a back-gate region of one second-conductivity typechannel MOS transistor comprising the CMOS transistor and theabove-described offset drain region 27 is formed at the same time theback-gate region of the other first-conductivity type channel MOStransistor comprising the CMOS transistor is formed. Specifically, whenthe high withstand voltage MOS transistor 21 is employed as onen-channel MOS transistor comprising the CMOS transistor, in the ionimplantation process of the n-type impurities to form the offset drainregion 27 shown in FIG. 4B, ions of the same n-type impurities 56 areimplanted on the region in which the n-type semiconductor well region(not shown) serving as the back-gate region of the other p-channel MOStransistor should be formed. Next, in the heat treatment process shownin FIG. 5A, the p-type semiconductor well region (back-gate region) 26of the n-channel MOS transistor 21, the offset drain region 27 formed ofthe n⁻ semiconductor region and the n-type semiconductor well region(back-gate region, not shown) of the p-channel MOS transistor are formedat the same time. The semiconductor device including the CMOS transistoris manufactured through the existing processes.

According to the high withstand voltage MOS transistor 21 including theoffset drain structure according to this embodiment, since thelightly-doped offset drain region (n⁻ semiconductor region) 27comprising the portion that does not overlap the p-type semiconductorwell region 26 and the portion that overlaps part of the surface of thep-type semiconductor well region 26 is formed, the heavily-dopedimpurity region formed at portion of the surface of the p-typesemiconductor well region 26 beneath the gate insulating film 29,accordingly, formed at portion of the channel region 28C is canceled bythe portion in which the offset drain region overlaps the p-typesemiconductor well region 26 and thereby removed. Thus, the whole of thechannel region 28C formed of the p-type semiconductor well regionbetween the source region 28S and the offset drain region 27 is formedwith a uniform low concentration. Accordingly, the threshold voltage Vthcan be prevented from becoming larger than a design value or can beprevented from being fluctuated so that a stable threshold voltage Vthcan be obtained and that a stable low ON-state resistance can beobtained. That is, there can be realized the highly-efficient and highwithstand voltage MOS transistor in which the high withstand voltage,the stable threshold voltage Vth and the low ON-state resistance arecompatible.

When the MOS transistor 21 is applied to the CMOS transistor, the MOStransistor 21 having this offset drain structure is formed as onen-channel MOS transistor comprising the CMOS transistor and the offsetdrain region (n⁻ semiconductor region) 27 of this n-channel MOStransistor 21 is formed at the same time the n-type semiconductor wellregion that serves as the back-gate electrode of the other p-channel MOStransistor comprising the CMOS transistor is formed, whereby the highwithstand voltage CMOS transistor can be obtained by the number ofexisting processes without increasing the processes.

Further, since the manufacturing method of the high withstand voltageaccording to this embodiment includes a series of the above-mentionedprocesses, in particular, the process for forming the lightly-dopedoffset drain region 27 that comprises the portion that does not overlapthe p-type semiconductor well region serving as the back-gate region andthe portion that overlaps part of the surface of the p-typesemiconductor well region, the heavily-doped region formed at theabove-described one portion of the surface of the channel region side ofthe p-type semiconductor well region 26 is canceled by the offset drainregion 27 and hence the concentration in the channel region 28 formed ofthe p-type semiconductor well region 26 between the source region 28Sand the offset drain region 27 can be made uniform in the whole area.Accordingly, the highly-efficient and high withstand voltage MOStransistor 21 in which the high withstand voltage, the threshold voltageVth and the low ON-state resistance are compatible can be manufacturedeasily and stably.

When the manufacturing method of the above-described high withstandvoltage MOS transistor is applied to the manufacturing process of theCMOS transistor, the above-described p-type semiconductor well region 21serves as the back-gate electrode of one n-channel MOS transistorcomprising the CMOS transistor and the above-described offset drainregion 27 is formed at the same time the n-type semiconductor wellregion serving as the back-gate region of the other p-channel MOStransistor comprising the CMOS transistor is formed, whereby thesemiconductor device including the CMOS transistor having at least onen-channel MOS transistor as the offset drain structure having the stablethreshold voltage Vth and the low ON-state resistance can bemanufactured by the number of the existing processes.

1. A semiconductor device including an MOS transistor in which a secondconductivity type source region is formed on a first conductivity typesemiconductor region, an offset drain region is electrically connectedto a second conductivity type drain region and has an impurityconcentration lower than that of said drain region, said offset drainregion is composed of a portion that does not overlap said firstconductivity type semiconductor region and a portion that overlaps partof the surface of said first conductivity type semiconductor region,said offset drain region is formed by a second conductivity type regionat its portion that does not overlap said first conductivity typesemiconductor region, said offset drain region is formed by a firstconductivity type region having an impurity concentration lower thanthat of said first conductivity type semiconductor region at its portionthat overlaps part of the surface of said first conductivity typesemiconductor region and a gate electrode is formed on the surfaceextending from a channel region between said source region and saidoffset drain region to part of said offset drain region through a gateinsulating film.
 2. A semiconductor device according to claim 1, whereinsaid MOS transistor is formed as one of second conductivity type channelMOS transistors comprising a CMOS transistor, said first conductivitytype semiconductor region serves as a back-gate region of said secondconductivity type channel MOS transistor and said offset drain region isformed at the same time the back-gate region of the first conductivitytype channel MOS transistor comprising said CMOS transistor is formed.3. A semiconductor device according to claim 1, further comprising afirst conductivity type element isolating layer formed beneath aisolation region for separating said MOS transistor at the same timesaid first conductivity type semiconductor region is formed.
 4. Asemiconductor device according to claim 3, wherein said isolation regionis formed of a field insulating layer by selective oxidation and saidfirst conductivity type semiconductor region and said first conductivitytype element isolation layer are formed by implanting ions such that thesemiconductor surface beneath said field insulating layer reaches a peakof an impurity concentration.
 5. A semiconductor device according toclaim 1, wherein said first conductivity type semiconductor region hason its surface formed a channel region the whole area of which is formedwith a uniform concentration.
 6. A semiconductor device manufacturingmethod comprising the steps of a process for forming a isolation regionfor separating an element forming region on a semiconductor substrate, aprocess for forming a first conductivity type semiconductor region onsaid element forming region, a process for forming an offset drainregion composed of a portion that does not overlap said firstconductivity type semiconductor region and a portion that overlaps partof the surface of said first conductivity type semiconductor region andwhich has an impurity concentration lower than that of a drain region, aprocess for forming second conductivity type source region and drainregion on said first conductivity semiconductor region and said offsetdrain region, respectively, and a process for forming a gate electrodeon the surface extending from a channel region composed of said firstconductivity type semiconductor region between said source region andsaid offset drain region to said offset drain region through a gateinsulating film.
 7. A semiconductor device manufacturing methodcomprising the steps of a process for forming a field insulating layerby selective oxidation for isolating an element forming region after asecond conductivity type buried region had been formed on a firstconductivity type semiconductor substrate and a second conductivity typeepitaxial layer had been formed, a process for forming a firstconductivity type semiconductor region on said element forming region, aprocess for forming an offset drain region by implanting secondconductivity type impurities over a portion that does not overlap saidfirst conductivity type semiconductor region and a portion that overlapspart of the surface of said first conductivity type semiconductor regionsuch that the portion that does not overlap said first conductivity typesemiconductor region serves as a second conductivity type region havingan impurity concentration lower than that of a drain region and theportion that overlaps part of the surface of said first conductivitytype semiconductor region serves as a first conductivity type regionhaving an impurity concentration lower than that of said firstconductivity type semiconductor region, a process for forming secondconductivity type source region and drain region on said firstconductivity type semiconductor region and said offset drain region,respectively, and a process for forming a gate electrode on the surfaceextending from a channel region composed of said first conductivity typesemiconductor region between said source region and said offset drainregion to said offset drain region through a gate insulating film.
 8. Asemiconductor device manufacturing method according to claim 6, whereinsaid offset drain region is formed at its portion that does not overlapsaid first conductivity type semiconductor region as a secondconductivity type region and said offset drain region is formed at itsportion that overlaps part of the surface of said first conductivitytype semiconductor region as a first conductivity region having animpurity concentration lower than that of said first conductivity typesemiconductor region.
 9. A semiconductor device manufacturing methodaccording to claim 7, wherein said first conductivity type semiconductorregion and said offset drain region are formed by implanting ions ofsecond conductivity type impurities and heat treatment of activationafter ions of first conductivity type impurities had been implanted. 10.A semiconductor device manufacturing method according to claim 9,wherein ions of second conductivity type impurities are implanted with adose large enough to cancel an impurity concentration peak portion onthe surface after ions of said first conductivity type impurities hadbeen implanted.
 11. A semiconductor device manufacturing methodaccording to claim 7, wherein said first conductivity type semiconductorregion and said offset drain region are formed by implanting ions offirst conductivity type impurities the dose of which lies in a range offrom 1×10¹³ to 1×10¹⁴ cm⁻² and by implanting ions of second conductivitytype impurities the dose of which lies in a range of from 5×10¹² to1×10¹⁴ cm⁻² and said second conductivity type source region and drainregion are formed by implanting ions of second conductivity typeimpurities the dose of which lies in a range of from 1×10¹⁵ to 1×10¹⁶cm⁻².
 12. A semiconductor device according to claim 6, wherein saidfirst conductivity type semiconductor region and a first conductivitytype element separation layer beneath said separation region are formedat the same time.
 13. A semiconductor device according to claim 12,wherein said first conductivity type semiconductor region and the firstconductivity type element separation layer beneath said isolation regionare formed at the same time by introducing first conductivity typeimpurities such that the semiconductor surface beneath said isolationregion reaches a peak of impurity concentration when ions are implanted.14. A semiconductor device manufacturing method according to claim 7,wherein said first conductivity type semiconductor region, the firstconductivity type element isolation layer beneath said isolation regionand said offset drain region are formed at the same time by implantingions of first conductivity type impurities through a positive typeresist mask the opening end portion of which is tapered and byimplanting ions of second conductivity type impurities through apositive type resist mask the opening end portion of which is tapered.15. A semiconductor device manufacturing method according to claim 6,wherein said first conductivity type semiconductor region serves as aback-gate region of one second conductivity type channel MOS transistorcomprising a CMOS transistor and said offset drain region is formed atthe same time the back-gate region of the other first conductivity typechannel MOS transistor comprising said CMOS transistor is formed.
 16. Asemiconductor device manufacturing method according to claim 7, whereinsaid first conductivity type semiconductor region serves as a back-gateregion of one second conductivity type channel MOS transistor comprisinga CMOS transistor and said offset drain region is formed at the sametime a back-gate region of the other first conductivity type channel MOStransistor comprising said CMOS transistor is formed.